ezusb.h Source File

00001 /***************************************************************************
00002                           ezusb.h  -  description
00003                              -------------------
00004     begin                : Sat Sep 2 2000
00005     copyright            : (C) 2000 by William Rachelson
00006     email                : gurufool@cc.gatech.edu
00007 
00008                 ezusb.h is intended for use with SDCC and Anchorchips' EZ-USB.  It is
00009         based on Anchor's ezusb.h file that was intended for the Keil compiler,
00010         and also on the standard 8051.h templates for SDCC.
00011 
00012  ***************************************************************************/
00013 
00014 /***************************************************************************
00015  *                                                                         *
00016  *   This program is free software; you can redistribute it and/or modify  *
00017  *   it under the terms of the GNU General Public License as published by  *
00018  *   the Free Software Foundation; either version 2 of the License, or     *
00019  *   (at your option) any later version.                                   *
00020  *                                                                         *
00021  ***************************************************************************/
00022 
00032 #ifndef EZUSB_H
00033 #define EZUSB_H
00034 
00035 
00036 //-----------------------------------------------------------------------------
00037 // Constants
00038 //-----------------------------------------------------------------------------
00039 #define TRUE    1
00040 #define FALSE   0
00041 
00042 #define bmBIT0  0x01
00043 #define bmBIT1  0x02
00044 #define bmBIT2  0x04
00045 #define bmBIT3  0x08
00046 #define bmBIT4  0x10
00047 #define bmBIT5  0x20
00048 #define bmBIT6  0x40
00049 #define bmBIT7  0x80
00050 
00051 #define DEVICE_DSCR             0x01            // Descriptor type: Device
00052 #define CONFIG_DSCR             0x02            // Descriptor type: Configuration
00053 #define STRING_DSCR             0x03            // Descriptor type: String
00054 #define INTRFC_DSCR             0x04            // Descriptor type: Interface
00055 #define ENDPNT_DSCR             0x05            // Descriptor type: End Point
00056 
00057 #define bmBUSPWR        bmBIT7                  // Config. attribute: Bus powered
00058 #define bmSELFPWR       bmBIT6                  // Config. attribute: Self powered
00059 #define bmRWU           bmBIT5                  // Config. attribute: Remote Wakeup
00060 
00061 #define bmEPOUT         bmBIT7
00062 #define bmEPIN          0x00
00063 
00064 #define EP_CONTROL      0x00                    // End Point type: Control
00065 #define EP_ISO          0x01                    // End Point type: Isochronous
00066 #define EP_BULK         0x02                    // End Point type: Bulk
00067 #define EP_INT          0x03                    // End Point type: Interrupt
00068 
00069 #define SUD_SIZE                                8               // Setup data packet size
00070 
00071 #define SC_GET_STATUS                   0x00    // Setup command: Get Status
00072 #define SC_CLEAR_FEATURE                0x01    // Setup command: Clear Feature
00073 #define SC_RESERVED                             0x02    // Setup command: Reserved
00074 #define SC_SET_FEATURE                  0x03    // Setup command: Set Feature
00075 #define SC_SET_ADDRESS                  0x05    // Setup command: Set Address
00076 #define SC_GET_DESCRIPTOR               0x06    // Setup command: Get Descriptor
00077 #define SC_SET_DESCRIPTOR               0x07    // Setup command: Set Descriptor
00078 #define SC_GET_CONFIGURATION    0x08    // Setup command: Get Configuration
00079 #define SC_SET_CONFIGURATION    0x09    // Setup command: Set Configuration
00080 #define SC_GET_INTERFACE                0x0a    // Setup command: Get Interface
00081 #define SC_SET_INTERFACE                0x0b    // Setup command: Set Interface
00082 #define SC_SYNC_FRAME                   0x0c    // Setup command: Sync Frame
00083 #define SC_ANCHOR_LOAD                  0xa0    // Setup command: Anchor load
00084         
00085 #define GD_DEVICE                               0x01    // Get device descriptor: Device
00086 #define GD_CONFIGURATION                0x02    // Get device descriptor: Configuration
00087 #define GD_STRING                               0x03    // Get device descriptor: String
00088 
00089 #define GS_DEVICE                               0x80    // Get Status: Device
00090 #define GS_INTERFACE                    0x81    // Get Status: Interface
00091 #define GS_ENDPOINT                             0x82    // Get Status: End Point
00092 
00093 #define FT_DEVICE                               0x00    // Feature: Device
00094 #define FT_ENDPOINT                             0x02    // Feature: End Point
00095 
00096 #define I2C_IDLE                                0               // I2C Status: Idle mode
00097 #define I2C_SENDING                             1               // I2C Status: I2C is sending data
00098 #define I2C_RECEIVING                   2               // I2C Status: I2C is receiving data
00099 #define I2C_PRIME                               3               // I2C Status: I2C is receiving the first byte of a string
00100 #define I2C_STOP                                5               // I2C Status: I2C waiting for stop completion
00101 #define I2C_BERROR                              6               // I2C Status: I2C error; Bit Error
00102 #define I2C_NACK                                7               // I2C Status: I2C error; No Acknowledge
00103 #define I2C_OK                                  8               // I2C positive return code
00104 
00105 
00106 
00107 
00108 /*-----------------------------------------------------------------------------
00109         Macros
00110 -----------------------------------------------------------------------------*/
00111 #define MSB(word)               (BYTE)(((WORD)word >> 8) & 0xff)
00112 #define LSB(word)               (BYTE)((WORD)word & 0xff)
00113 
00114 #define SWAP_ENDIAN(word)       ((BYTE*)&word)[0] ^= ((BYTE*)&word)[1];\
00115                                                         ((BYTE*)&word)[1] ^= ((BYTE*)&word)[0];\
00116                                                         ((BYTE*)&word)[0] ^= ((BYTE*)&word)[1]
00117 
00118 #define EZUSB_IRQ_ENABLE()      EUSB = 1
00119 #define EZUSB_IRQ_DISABLE()     EUSB = 0
00120 #ifndef CHIPREV_B
00121 #define EZUSB_IRQ_CLEAR()       EXIF &= ~0x10           // IE2_
00122 #endif
00123 
00124 #define EZUSB_STALL_EP0()                               EP0CS |= bmEPSTALL
00125 #define EZUSB_STALL_EP(ep_id)                   EPIO[ep_id].cntrl = bmEPSTALL
00126 #define EZUSB_UNSTALL_EP(ep_id)                 EPIO[ep_id].cntrl = 0
00127 #define EZUSB_GET_EP_STATUS(ep_id)              EPIO[ep_id].cntrl
00128 #define EZUSB_SET_EP_BYTES(ep_id,count) EPIO[ep_id].bytes = count
00129 
00130 #define EZUSB_RESET_DATA_TOGGLE(ep)     TOGCTL = (((ep & 0x80) >> 3) + (ep & 0x07));\
00131                                         TOGCTL |= 0x20
00132 
00133 
00134 #define EZUSB_ENABLE_RSMIRQ()           (EICON |= 0x20)         // Enable Resume Interrupt (EPFI_)
00135 #define EZUSB_DISABLE_RSMIRQ()          (EICON &= ~0x20)        // Disable Resume Interrupt (EPFI_)
00136 #define EZUSB_CLEAR_RSMIRQ()            (EICON &= ~0x10)        // Clear Resume Interrupt Flag (PFI_)
00137 
00138 #define EZUSB_GETI2CSTATUS()            (I2CPckt.status)
00139 #define EZUSB_CLEARI2CSTATUS()          if((I2CPckt.status == I2C_BERROR) || (I2CPckt.status == I2C_NACK))\
00140                                                                                 I2CPckt.status = I2C_IDLE;
00141 
00142 #define EZUSB_ENABLEBP()                        (USBBAV |= bmBPEN)
00143 #define EZUSB_DISABLEBP()                       (USBBAV &= ~bmBPEN)
00144 #define EZUSB_CLEARBP()                         (USBBAV |= bmBREAK)
00145 #define EZUSB_BP(addr)                          BPADDR = (WORD)addr
00146 
00147 #define EZUSB_EXTWAKEUP()                       (USBCS & bmRWAKEUP)
00148 
00149 /* Convert End point ID (d0000eee) to EPIO offset */
00150 #define EPID(id)                (((~id & 0x80) >> 4) + (id & 0x07))
00151 
00152 
00153 
00154 //-----------------------------------------------------------------------------
00155 // Datatypes
00156 //-----------------------------------------------------------------------------
00157 typedef unsigned char   BYTE;
00158 typedef unsigned short  WORD;
00159 typedef unsigned long   DWORD;
00160 typedef bit                             BOOL;
00161 
00162 #define INT0_VECT       0
00163 #define TMR0_VECT       1
00164 #define INT1_VECT       2
00165 #define TMR1_VECT       3
00166 #define COM0_VECT       4
00167 #define TMR2_VECT       5
00168 #define WKUP_VECT       6
00169 #define COM1_VECT       7
00170 #define USB_VECT        8
00171 #define I2C_VECT        9
00172 #define INT4_VECT       10
00173 #define INT5_VECT       11
00174 #define INT6_VECT       12
00175 
00176 #define SUDAV_USBVECT   (0 << 2)
00177 #define SOF_USBVECT             (1 << 2)
00178 #define SUTOK_USBVECT   (2 << 2)
00179 #define SUSP_USBVECT    (3 << 2)
00180 #define URES_USBVECT    (4 << 2)
00181 #define SPARE_USBVECT   (5 << 2)
00182 #define IN0BUF_USBVECT  (6 << 2)
00183 #define OUT0BUF_USBVECT (7 << 2)
00184 #define IN1BUF_USBVECT  (8 << 2)
00185 #define OUT1BUF_USBVECT (9 << 2)
00186 #define IN2BUF_USBVECT  (10 << 2)
00187 #define OUT2BUF_USBVECT (11 << 2)
00188 #define IN3BUF_USBVECT  (12 << 2)
00189 #define OUT3BUF_USBVECT (13 << 2)
00190 #define IN4BUF_USBVECT  (14 << 2)
00191 #define OUT4BUF_USBVECT (15 << 2)
00192 #define IN5BUF_USBVECT  (16 << 2)
00193 #define OUT5BUF_USBVECT (17 << 2)
00194 #define IN6BUF_USBVECT  (18 << 2)
00195 #define OUT6BUF_USBVECT (19 << 2)
00196 #define IN7BUF_USBVECT  (20 << 2)
00197 #define OUT7BUF_USBVECT (21 << 2)
00198 
00200 typedef struct
00201 {
00202         BYTE    length;
00203         BYTE    type;
00204 }DSCR;
00205 
00207 typedef struct                          // Device Descriptor
00208 {
00209         BYTE    length;                 // Descriptor length ( = sizeof(DEVICEDSCR) )
00210         BYTE    type;                   // Decriptor type (Device = 1)
00211         BYTE    spec_ver_minor; // Specification Version (BCD) minor
00212         BYTE    spec_ver_major; // Specification Version (BCD) major
00213         BYTE    dev_class;              // Device class
00214         BYTE    sub_class;              // Device sub-class
00215         BYTE    protocol;               // Device sub-sub-class
00216         BYTE    max_packet;             // Maximum packet size
00217         WORD    vendor_id;              // Vendor ID
00218         WORD    product_id;             // Product ID
00219         WORD    version_id;             // Product version ID
00220         BYTE    mfg_str;                // Manufacturer string index
00221         BYTE    prod_str;               // Product string index
00222         BYTE    serialnum_str;  // Serial number string index
00223         BYTE    configs;                // Numder of configurations
00224 }DEVICEDSCR;
00225 
00227 typedef struct
00228 {
00229         BYTE    length;                 // Configuration length ( = sizeof(CONFIGDSCR) )
00230         BYTE    type;                   // Descriptor type (Configuration = 2)
00231         WORD    config_len;             // Configuration + End Points length
00232         BYTE    interfaces;             // Number of interfaces
00233         BYTE    index;                  // Configuration number
00234         BYTE    config_str;             // Configuration string
00235         BYTE    attrib;                 // Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu
00236         BYTE    power;                  // Power requirement (div 2 ma)
00237 }CONFIGDSCR;
00238 
00240 typedef struct
00241 {
00242         BYTE    length;                 // Interface descriptor length ( - sizeof(INTRFCDSCR) )
00243         BYTE    type;                   // Descriptor type (Interface = 4)
00244         BYTE    index;                  // Zero-based index of this interface
00245         BYTE    alt_setting;    // Alternate setting
00246         BYTE    ep_cnt;                 // Number of end points
00247         BYTE    class;                  // Interface class
00248         BYTE    sub_class;              // Interface sub class
00249         BYTE    protocol;               // Interface sub sub class
00250         BYTE    interface_str;  // Interface descriptor string index
00251 }INTRFCDSCR;
00252 
00254 typedef struct
00255 {
00256         BYTE    length;                 // End point descriptor length ( = sizeof(ENDPNTDSCR) )
00257         BYTE    type;                   // Descriptor type (End point = 5)
00258         BYTE    addr;                   // End point address
00259         BYTE    ep_type;                // End point type
00260         BYTE    mp_L;                   // Maximum packet size
00261         BYTE    mp_H;
00262         BYTE    interval;               // Interrupt polling interval
00263 }ENDPNTDSCR;
00264 
00266 typedef struct
00267 {
00268         BYTE    length;                 // String descriptor length
00269         BYTE    type;                   // Descriptor type
00270 }STRINGDSCR;
00271 
00273 typedef struct
00274 {
00275         BYTE    cntrl;                  // End point control register
00276         BYTE    bytes;                  // End point buffer byte count
00277 }EPIOC;
00278 
00280 typedef struct
00281 {
00282         BYTE    length;
00283         BYTE    *dat;
00284         BYTE    count;
00285         BYTE    status;
00286 }I2CPCKT;
00287 
00288 
00289 
00290 /*-----------------------------------------------------------------------------
00291         Global Variables
00292         The Ez-USB registers are defined here.
00293 -----------------------------------------------------------------------------*/
00294 
00295 xdata volatile BYTE at  0x7B40   OUT7BUF[64]    ;
00296 xdata volatile BYTE at  0x7B80   IN7BUF[64]     ;
00297 xdata volatile BYTE at  0x7BC0   OUT6BUF[64]    ;
00298 xdata volatile BYTE at  0x7C00   IN6BUF[64]     ;
00299 xdata volatile BYTE at  0x7C40   OUT5BUF[64]    ;
00300 xdata volatile BYTE at  0x7C80   IN5BUF[64]     ;
00301 xdata volatile BYTE at  0x7CC0   OUT4BUF[64]    ;
00302 xdata volatile BYTE at  0x7D00   IN4BUF[64]     ;
00303 xdata volatile BYTE at  0x7D40   OUT3BUF[64]    ;
00304 xdata volatile BYTE at  0x7D80   IN3BUF[64]     ;
00305 xdata volatile BYTE at  0x7DC0   OUT2BUF[64]    ;
00306 xdata volatile BYTE at  0x7E00   IN2BUF[64]     ;
00307 xdata volatile BYTE at  0x7E40   OUT1BUF[64]    ;
00308 xdata volatile BYTE at  0x7E80   IN1BUF[64]     ;
00309 xdata volatile BYTE at  0x7EC0   OUT0BUF[64]    ;
00310 xdata volatile BYTE at  0x7F00   IN0BUF[64]     ;
00311 xdata volatile BYTE at  0x7F60   OUT8DATA       ;
00312 xdata volatile BYTE at  0x7F61   OUT9DATA       ;
00313 xdata volatile BYTE at  0x7F62   OUT10DATA      ;
00314 xdata volatile BYTE at  0x7F63   OUT11DATA      ;
00315 xdata volatile BYTE at  0x7F64   OUT12DATA      ;
00316 xdata volatile BYTE at  0x7F65   OUT13DATA      ;
00317 xdata volatile BYTE at  0x7F66   OUT14DATA      ;
00318 xdata volatile BYTE at  0x7F67   OUT15DATA      ;
00319 xdata volatile BYTE at  0x7F68   IN8DATA        ;
00320 xdata volatile BYTE at  0x7F69   IN9DATA        ;
00321 xdata volatile BYTE at  0x7F6A   IN10DATA       ;
00322 xdata volatile BYTE at  0x7F6B   IN11DATA       ;
00323 xdata volatile BYTE at  0x7F6C   IN12DATA       ;
00324 xdata volatile BYTE at  0x7F6D   IN13DATA       ;
00325 xdata volatile BYTE at  0x7F6E   IN14DATA       ;
00326 xdata volatile BYTE at  0x7F6F   IN15DATA       ;
00327 xdata volatile BYTE at  0x7F70   OUT8BCH        ;
00328 xdata volatile BYTE at  0x7F71   OUT8BCL        ;
00329 xdata volatile BYTE at  0x7F72   OUT9BCH        ;
00330 xdata volatile BYTE at  0x7F73   OUT9BCL        ;
00331 xdata volatile BYTE at  0x7F74   OUT10BCH       ;
00332 xdata volatile BYTE at  0x7F75   OUT10BCL       ;
00333 xdata volatile BYTE at  0x7F76   OUT11BCH       ;
00334 xdata volatile BYTE at  0x7F77   OUT11BCL       ;
00335 xdata volatile BYTE at  0x7F78   OUT12BCH       ;
00336 xdata volatile BYTE at  0x7F79   OUT12BCL       ;
00337 xdata volatile BYTE at  0x7F7A   OUT13BCH       ;
00338 xdata volatile BYTE at  0x7F7B   OUT13BCL       ;
00339 xdata volatile BYTE at  0x7F7C   OUT14BCH       ;
00340 xdata volatile BYTE at  0x7F7D   OUT14BCL       ;
00341 xdata volatile BYTE at  0x7F7E   OUT15BCH       ;
00342 xdata volatile BYTE at  0x7F7F   OUT15BCL       ;
00343 xdata volatile BYTE at  0x7F90   SPARE1         ;
00344 xdata volatile BYTE at  0x7F91   SPARE2         ;
00345 xdata volatile BYTE at  0x7F92   CPUCS          ;
00346 xdata volatile BYTE at  0x7F93   PORTACFG       ;
00347 xdata volatile BYTE at  0x7F94   PORTBCFG       ;
00348 xdata volatile BYTE at  0x7F95   PORTCCFG       ;
00349 xdata volatile BYTE at  0x7F96   OUTA   ;
00350 xdata volatile BYTE at  0x7F97   OUTB   ;
00351 xdata volatile BYTE at  0x7F98   OUTC   ;
00352 xdata volatile BYTE at  0x7F99   PINSA          ;
00353 xdata volatile BYTE at  0x7F9A   PINSB          ;
00354 xdata volatile BYTE at  0x7F9B   PINSC          ;
00355 xdata volatile BYTE at  0x7F9C   OEA    ;
00356 xdata volatile BYTE at  0x7F9D   OEB    ;
00357 xdata volatile BYTE at  0x7F9E   OEC    ;
00358 xdata volatile BYTE at  0x7F9F   SPARE3         ;
00359 xdata volatile BYTE at  0x7FA0   ISOERR         ;
00360 xdata volatile BYTE at  0x7FA1   ISOCTL         ;
00361 xdata volatile BYTE at  0x7FA2   ZBCOUT         ;
00362 xdata volatile BYTE at  0x7FA3   ZBCIN          ;
00363 xdata volatile BYTE at  0x7FA4   SPARE4         ;
00364 xdata volatile BYTE at  0x7FA5   I2CS   ;
00365 xdata volatile BYTE at  0x7FA6   I2DAT          ;
00366 xdata volatile BYTE at  0x7FA7   SPARE5         ;
00367 xdata volatile BYTE at  0x7FA8   IVEC   ;
00368 xdata volatile BYTE at  0x7FA9   IN07IRQ        ;
00369 xdata volatile BYTE at  0x7FAA   OUT07IRQ       ;
00370 xdata volatile BYTE at  0x7FAB   USBIRQ         ;
00371 xdata volatile BYTE at  0x7FAC   IN07IEN        ;
00372 xdata volatile BYTE at  0x7FAD   OUT07IEN       ;
00373 xdata volatile BYTE at  0x7FAE   USBIEN         ;
00374 xdata volatile BYTE at  0x7FAF   USBBAV         ;
00375 xdata volatile WORD at  0x7FB0   AVADDR         ;
00376 xdata volatile WORD at  0x7FB2    BPADDR        ;
00377 xdata volatile BYTE at  0x7FB3   BPADDRL        ;
00378 xdata volatile EPIOC at 0x7FB4   EPIO[16]       ;
00379 xdata volatile BYTE at  0x7FD4   SUDPTRH        ;
00380 xdata volatile BYTE at  0x7FD5   SUDPTRL        ;
00381 xdata volatile BYTE at  0x7FD6   USBCS          ;
00382 xdata volatile BYTE at  0x7FD7   TOGCTL         ;
00383 xdata volatile BYTE at  0x7FD8   USBFRAMEL      ;
00384 xdata volatile BYTE at  0x7FD9   USBFRAMEH      ;
00385 xdata volatile BYTE at  0x7FDA   SPARE6         ;
00386 xdata volatile BYTE at  0x7FDB   FNADDR         ;
00387 xdata volatile BYTE at  0x7FDC   SPARE7         ;
00388 xdata volatile BYTE at  0x7FDD   USBPAIR        ;
00389 xdata volatile BYTE at  0x7FDE   IN07VAL        ;
00390 xdata volatile BYTE at  0x7FDF   OUT07VAL       ;
00391 xdata volatile BYTE at  0x7FE0   INISOVAL       ;
00392 xdata volatile BYTE at  0x7FE1   OUTISOVAL      ;
00393 xdata volatile BYTE at  0x7FE2   FASTXFR        ;
00394 xdata volatile BYTE at  0x7FE3   AUTOPTRH       ;
00395 xdata volatile BYTE at  0x7FE4   AUTOPTRL       ;
00396 xdata volatile BYTE at  0x7FE5   AUTODATA       ;
00397 xdata volatile BYTE at  0x7FE6   SPARE8         ;
00398 xdata volatile BYTE at  0x7FE7   SPARE9         ;
00399 xdata volatile BYTE at  0x7FE8   SETUPDAT[8]    ;
00400 xdata volatile BYTE at  0x7FF0   OUT8ADDR       ;
00401 xdata volatile BYTE at  0x7FF1   OUT9ADDR       ;
00402 xdata volatile BYTE at  0x7FF2   OUT10ADDR      ;
00403 xdata volatile BYTE at  0x7FF3   OUT11ADDR      ;
00404 xdata volatile BYTE at  0x7FF4   OUT12ADDR      ;
00405 xdata volatile BYTE at  0x7FF5   OUT13ADDR      ;
00406 xdata volatile BYTE at  0x7FF6   OUT14ADDR      ;
00407 xdata volatile BYTE at  0x7FF7   OUT15ADDR      ;
00408 xdata volatile BYTE at  0x7FF8   IN8ADDR        ;
00409 xdata volatile BYTE at  0x7FF9   IN9ADDR        ;
00410 xdata volatile BYTE at  0x7FFA   IN10ADDR       ;
00411 xdata volatile BYTE at  0x7FFB   IN11ADDR       ;
00412 xdata volatile BYTE at  0x7FFC   IN12ADDR       ;
00413 xdata volatile BYTE at  0x7FFD   IN13ADDR       ;
00414 xdata volatile BYTE at  0x7FFE   IN14ADDR       ;
00415 xdata volatile BYTE at  0x7FFF   IN15ADDR       ;
00416 
00417 
00418 
00419 /*-----------------------------------------------------------------------------
00420         Special Function Registers (sfr at 0xs)
00421         The byte registers and bits defined in the following list are based
00422         on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
00423     If you modify the register definitions below, please regenerate the file
00424     "ezregs.inc" which includes the same basic information for assembly inclusion.
00425 -----------------------------------------------------------------------------*/
00426 
00427 sfr at 0x81 SP          ;   // Stack Pointer
00428 sfr at 0x82 DPL         ;   // Data Pointer Low
00429 sfr at 0x83 DPH         ;               // Data Pointer High
00430 sfr at 0x84 DPL1        ;
00431 sfr at 0x85 DPH1        ;
00432 sfr at 0x86 DPS         ;
00433         /*  DPS  */
00434 sbit at 0x86 SEL        ;
00435 
00436 
00437 /*  PCON  */
00438 sfr at 0x87 PCON;
00439 sbit at 0x87 IDLE;
00440 sbit at 0x88 STOP;
00441 sbit at 0x89 GF0;
00442 sbit at 0x9A GF1;
00443 sbit at 0x9B SMOD0;
00444 
00445 /*  TCON  */
00446 sfr at 0x88 TCON        ;
00447 sbit at 0x88 IT0;
00448 sbit at 0x89 IE0;
00449 sbit at 0x8A IT1;
00450 sbit at 0x8B IE1;
00451 sbit at 0x8C TR0;
00452 sbit at 0x8D TF0;
00453 sbit at 0x8E TR1;
00454 sbit at 0x8F TF1;
00455 
00456 /*  TMOD  */
00457 sfr at 0x89 TMOD;
00458         //sbit at 0x M00    = 0x89+0;
00459         //sbit at 0x M10    = 0x89+1;
00460         //sbit at 0x CT0    = 0x89+2;
00461         //sbit at 0x GATE0  = 0x89+3;
00462         //sbit at 0x M01    = 0x89+4;
00463         //sbit at 0x M11    = 0x89+5;
00464         //sbit at 0x CT1    = 0x89+6;
00465         //sbit at 0x GATE1  = 0x89+7;
00466 sfr at 0x8A TL0;
00467 sfr at 0x8B TL1;
00468 sfr at 0x8C TH0;
00469 sfr at 0x8D TH1;
00470 
00471 /*  CKCON  */
00472 sfr at 0x8E CKCON;
00473 sbit at 0x8E MD0;
00474 sbit at 0x8F MD1;
00475 sbit at 0x90 MD2;
00476 sbit at 0x91 T0M;
00477 sbit at 0x92 T1M;
00478 sbit at 0x93 T2M;
00479 
00480 sfr at 0x8F SPC_FNC; // Was WRS in Reg320
00481         /*  CKCON  */
00482         //sbit at 0x WRS    = 0x8F+0;
00483 sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320
00484         /*  EXIF  */
00485         //sbit at 0x USBINT = 0x91+4;
00486         //sbit at 0x I2CINT = 0x91+5;
00487         //sbit at 0x IE4    = 0x91+6;
00488         //sbit at 0x IE5    = 0x91+7;
00489 sfr at 0x92 MPAGE;
00490 
00491 /*  SCON0  */
00492 sfr at 0x98 SCON0;
00493 sbit at 0x98 RI;
00494 sbit at 0x99 TI;
00495 sbit at 0x9A RB8;
00496 sbit at 0x9B TB8;
00497 sbit at 0x9C REN;
00498 sbit at 0x9D SM2;
00499 sbit at 0x9E SM1;
00500 sbit at 0x9F SM0;
00501 
00502 sfr at 0x99 SBUF0;
00503 sfr at 0xA8 IE;
00504         /*  IE  */
00505         sbit at 0xA8 EX0;
00506         sbit at 0xA9 ET0;
00507         sbit at 0xAA EX1;
00508         sbit at 0xAB ET1;
00509         sbit at 0xAC ES0;
00510         sbit at 0xAD ET2;
00511         sbit at 0xAE ES1;
00512         sbit at 0xAF EA;
00513 
00514 /*  IP  */
00515 sfr at 0xB8 IP;
00516 sbit at 0xB8 PX0;
00517 sbit at 0xB9 PT0;
00518 sbit at 0xBA PX1;
00519 sbit at 0xBB PT1;
00520 sbit at 0xBC PS0;
00521 sbit at 0xBD PT2;
00522 sbit at 0xBE PS1;
00523 
00524 
00525 sfr at 0xC0 SCON1;
00526         /*  SCON1  */
00527         sbit at 0xC0 RI1;
00528         sbit at 0xC1 TI1;
00529         sbit at 0xC2 RB81;
00530         sbit at 0xC3 TB81;
00531         sbit at 0xC4 REN1;
00532         sbit at 0xC5 SM21;
00533         sbit at 0xC6 SM11;
00534         sbit at 0xC7 SM01;
00535 sfr at 0xC1 SBUF1;
00536 sfr at 0xC8 T2CON;
00537         /*  T2CON  */
00538         sbit at 0xC8 CP_RL2;
00539         sbit at 0xC9 C_T2;
00540         sbit at 0xCA TR2;
00541         sbit at 0xCB EXEN2;
00542         sbit at 0xCC TCLK;
00543         sbit at 0xCD RCLK;
00544         sbit at 0xCE EXF2;
00545         sbit at 0xCF TF2;
00546 sfr at 0xCA RCAP2L;
00547 sfr at 0xCB RCAP2H;
00548 sfr at 0xCC TL2;
00549 sfr at 0xCD TH2;
00550 sfr at 0xD0 PSW;
00551         /*  PSW  */
00552         sbit at 0xD0 P;
00553         sbit at 0xD1 FL;
00554         sbit at 0xD2 OV;
00555         sbit at 0xD3 RS0;
00556         sbit at 0xD4 RS1;
00557         sbit at 0xD5 F0;
00558         sbit at 0xD6 AC;
00559         sbit at 0xD7 CY;
00560 sfr at 0xD8 EICON; // Was WDCON in DS80C320; Bit Values differ from Reg320
00561         /*  EICON  */
00562         sbit at 0xDB INT6;
00563         sbit at 0xDC RESI;
00564         sbit at 0xDE ERESI;
00565         sbit at 0xDF SMOD1;
00566 sfr at 0xE0 ACC;
00567 sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320
00568   /*  EIE  */
00569         sbit at 0xE8 EUSB;
00570         sbit at 0xE9 EI2C;
00571         sbit at 0xEA EIEX4;
00572         sbit at 0xEB EIEX5;
00573         sbit at 0xEC EIEX6;
00574 sfr at 0xF0 B;
00575 sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320
00576   /*  EIP  */
00577         sbit at 0xF8 PUSB;
00578         sbit at 0xF9 PI2C;
00579         sbit at 0xFA EIPX4;
00580         sbit at 0xFB EIPX5;
00581         sbit at 0xFC EIPX6;
00582 
00583 
00584 
00585 
00586 
00587 /*-----------------------------------------------------------------------------
00588         Bit Masks
00589 -----------------------------------------------------------------------------*/
00590 
00591 /* CPU Control & Status Register */
00592 #define bmCLK24OE               bmBIT1
00593 #define bm8052RES               bmBIT0
00594 /* Port Configuration Registers */
00595 /* Port A */
00596 #define bmRXD1OUT               bmBIT7
00597 #define bmRXD0OUT               bmBIT6
00598 #define bmFRD                   bmBIT5
00599 #define bmFWR                   bmBIT4
00600 #define bmCS                    bmBIT3
00601 #define bmOE                    bmBIT2
00602 #define bmT1OUT                 bmBIT1
00603 #define bmT0OUT                 bmBIT0
00604 /* Port B */
00605 #define bmT2OUT                 bmBIT7
00606 #define bmINT6                  bmBIT6
00607 #define bmINT5                  bmBIT5
00608 #define bmINT4                  bmBIT4
00609 #define bmTXD1                  bmBIT3
00610 #define bmRXD1                  bmBIT2
00611 #define bmT2EX                  bmBIT1
00612 #define bmT2                    bmBIT0
00613 /* Port C */
00614 #define bmRD                    bmBIT7
00615 #define bmWR                    bmBIT6
00616 #define bmT1                    bmBIT5
00617 #define bmT0                    bmBIT4
00618 #define bmINT1                  bmBIT3
00619 #define bmINT0                  bmBIT2
00620 #define bmTXD0                  bmBIT1
00621 #define bmRXD0                  bmBIT0
00622 /* Isochronous Status & End Point Valid Registers */
00623 #define bmEP15                  bmBIT7
00624 #define bmEP14                  bmBIT6
00625 #define bmEP13                  bmBIT5
00626 #define bmEP12                  bmBIT4
00627 #define bmEP11                  bmBIT3
00628 #define bmEP10                  bmBIT2
00629 #define bmEP9                   bmBIT1
00630 #define bmEP8                   bmBIT0
00631 /* I2C Control & Status Register */
00632 #define bmSTART                 bmBIT7
00633 #define bmSTOP                  bmBIT6
00634 #define bmLASTRD                bmBIT5
00635 #define bmID                    (bmBIT4 | bmBIT3)
00636 #define bmBERR                  bmBIT2
00637 #define bmACK                   bmBIT1
00638 #define bmDONE                  bmBIT0
00639 /* Interrupt Vector Register */
00640 #define bmIV4                   bmBIT6
00641 #define bmIV3                   bmBIT5
00642 #define bmIV2                   bmBIT4
00643 #define bmIV1                   bmBIT3
00644 #define bmIV0                   bmBIT2
00645 /* End point Interrupt Request, End Point Interrupt Enable */
00646 /* And End Point Valid Registers */
00647 #define bmEP7                   bmBIT7
00648 #define bmEP6                   bmBIT6
00649 #define bmEP5                   bmBIT5
00650 #define bmEP4                   bmBIT4
00651 #define bmEP3                   bmBIT3
00652 #define bmEP2                   bmBIT2
00653 #define bmEP1                   bmBIT1
00654 #define bmEP0                   bmBIT0
00655 /* Global Interrupt Request & Enable Registers */
00656 #define bmURES                  bmBIT4
00657 #define bmSUSP                  bmBIT3
00658 #define bmSUTOK                 bmBIT2
00659 #define bmSOF                   bmBIT1
00660 #define bmSUDAV                 bmBIT0
00661 /* Global Control */
00662 #define bmBREAK                 bmBIT3
00663 #define bmBPPULSE               bmBIT2
00664 #define bmBPEN                  bmBIT1
00665 #define bmAVEN                  bmBIT0
00666 /* USB Control & Status Register */
00667 #define bmRWAKEUP               bmBIT7
00668 #define bmDISCON                bmBIT3
00669 #define bmDISCOE                bmBIT2
00670 #define bmRENUM                 bmBIT1
00671 #define bmSIGRESUME             bmBIT0
00672 /* End Point 0 Control & Status Register */
00673 #define bmOUT                   bmBIT3
00674 #define bmIN                    bmBIT2
00675 #define bmHS                    bmBIT1
00676 #define bmHSSTALL               bmBIT0
00677 /* End Point Control & Status Registers */
00678 #define bmEPSTALL               bmBIT0
00679 #define bmEPBUSY                bmBIT1
00680 /* Fast Transfer Register */
00681 #define bmFISO                  bmBIT7
00682 #define bmFBLK                  bmBIT6
00683 #define bmRPOL                  bmBIT5
00684 #define bmRMOD1                 bmBIT4
00685 #define bmRMOD0                 bmBIT3
00686 #define bmWPOL                  bmBIT2
00687 #define bmWMOD1                 bmBIT1
00688 #define bmWMOD0                 bmBIT0
00689 /* Endpoint Pairing Register */
00690 #define bmISOSEND0              bmBIT7
00691 #define bmPR6OUT                bmBIT5
00692 #define bmPR4OUT                bmBIT4
00693 #define bmPR2OUT                bmBIT3
00694 #define bmPR6IN                 bmBIT2
00695 #define bmPR4IN                 bmBIT1
00696 #define bmPR2IN                 bmBIT0
00697 /* End point control offsets */
00698 
00699 /* What is this for? */
00700 enum
00701 {
00702         IN0BUF_ID = 0,
00703         IN1BUF_ID,
00704         IN2BUF_ID,
00705         IN3BUF_ID,
00706         IN4BUF_ID,
00707         IN5BUF_ID,
00708         IN6BUF_ID,
00709         IN7BUF_ID,
00710         OUT0BUF_ID,
00711         OUT1BUF_ID,
00712         OUT2BUF_ID,
00713         OUT3BUF_ID,
00714         OUT4BUF_ID,
00715         OUT5BUF_ID,
00716         OUT6BUF_ID,
00717         OUT7BUF_ID
00718 };
00719 
00720 
00721 /* What are these for? */
00722 #define EP0CS   EPIO[0].cntrl
00723 #define IN0BC   EPIO[0].bytes
00724 #define IN1CS   EPIO[1].cntrl
00725 #define IN1BC   EPIO[1].bytes
00726 #define IN2CS   EPIO[2].cntrl
00727 #define IN2BC   EPIO[2].bytes
00728 #define IN3CS   EPIO[3].cntrl
00729 #define IN3BC   EPIO[3].bytes
00730 #define IN4CS   EPIO[4].cntrl
00731 #define IN4BC   EPIO[4].bytes
00732 #define IN5CS   EPIO[5].cntrl
00733 #define IN5BC   EPIO[5].bytes
00734 #define IN6CS   EPIO[6].cntrl
00735 #define IN6BC   EPIO[6].bytes
00736 #define IN7CS   EPIO[7].cntrl
00737 #define IN7BC   EPIO[7].bytes
00738 #define OUT0CS  EPIO[8].cntrl
00739 #define OUT0BC  EPIO[8].bytes
00740 #define OUT1CS  EPIO[9].cntrl
00741 #define OUT1BC  EPIO[9].bytes
00742 #define OUT2CS  EPIO[10].cntrl
00743 #define OUT2BC  EPIO[10].bytes
00744 #define OUT3CS  EPIO[11].cntrl
00745 #define OUT3BC  EPIO[11].bytes
00746 #define OUT4CS  EPIO[12].cntrl
00747 #define OUT4BC  EPIO[12].bytes
00748 #define OUT5CS  EPIO[13].cntrl
00749 #define OUT5BC  EPIO[13].bytes
00750 #define OUT6CS  EPIO[14].cntrl
00751 #define OUT6BC  EPIO[14].bytes
00752 #define OUT7CS  EPIO[15].cntrl
00753 #define OUT7BC  EPIO[15].bytes
00754 
00755 #endif