ARM Development at LAP

<body> <table><tr> <td> <div align=center><a href="../index.html" target="_top"><img src="images/logo-lap.png" border="0" alt="Logo LAP"></a></div><br><b><a href="index.php?presentation" target="_top">Présentation</a></b><br><br><b><a href="index.php?cpuboards" target="_top">CPU/FPGA boards</a></b><br><ul> <li><a href="index.php?armonie" target="_top">Armonie</a><li><a href="index.php?rokepxa1" target="_top">RokEPXA</a><li><a href="index.php?epxa4usb2" target="_top">EPXA4-USB2</a></ul> <br><b><a href="index.php?boards" target="_top">Add-on boards</a></b><br><br><b><a href="index.php?tools" target="_top">Development tools</a></b><br><br><b><a href="index.php?spec" target="_top">Specifications</a></b><br><br><b><a href="index.php?contact" target="_top">Contact</a></b><br></td> <td> <center> <H1>RokEPXA</h1> <h3>Robot Kit with an EPXA1</h3> </center> <P> RokEPXA is a minimal board using A-BUS compatible power-supply. This board can be used with a little robot base called Cyclope. RokEPXA replaces old main boards RokHC12 and Rok68 of the robot Cyclope and opens a new era. Alera EPXA integreted circuit contains an "hardcore" ARM922T processor system and a FPGA. This board can not only be used with the robot Cyclope but in many others applications. Now, it's possible to build a multi-processor system using Altera NIOS "softcore" processor system in FPGA, for example. </p> <center> <table> <tr><td width="400" align="center"> <img width="300" src="images/cyclope_abus_rokepxa_small.jpg" alt="RokEPXA with the robot Cyclope and the magic A-BUS power supply" border="0"> </td><td width="500" align="center"> <img width="400" src="images/rokepxa_top_small.jpg" alt="RokEPXA top side" border="0"> </td></tr> <tr> <td align="center"><small>RokEPXA and A-BUS power supply boards with the robot Cyclope base</small></td> <td align="center"><small>RokEPXA top side</small></td> </tr> </table> </center> <P> RokEPXA features: <ul> <li>Dimensions 10 cm x 7.8 cm</li> <li>EPXA1 contains a complete ARM922T processor system with a SDRAM memory controller, an expansion bus interface, an UART, a timer, two blocks of SRAM, a dual ported memory and two bridges for communication with FPGA part</li> <li>64 MB of dynamic memory (2 x 32MB x 8 bits SDRAM/DDR266) </li> <li>8 MB of FLASH memory (Intel StrataFLASH)</li> <li>Two connectors compatible with Milli-BUS specification</li> <li>MuBUS connector</li> <li>Camera2D connector for little mono/<font color="#ff0000">c</font><font color="#00ff00">ol</font><font color="#0000ff">our</font> CMOS cameras with a digital interface</li> <li>SPI connector</li> <li>USB slave connector with the tranceiver</li> <li>Two RS-232 LVTTL level connectors (without transceiver, levels are between 0V and +3.3V)</li> <li>Two JTAG connectors, one for each JTAG TAP in EPXA1</li> <li>Two I²C connectors</li> <li>Two A-BUS compatible connectors for power supply</li> </ul> </p> </td> </tr> <tr><td colspan=2><hr></td></tr> <tr><td colspan=2 align=center><small>Last page update : 2003</small></td></tr> </table> </body>