Jelie 1.4

free software for XScale developement

What is Jelie ?

Jelie is a JTAG port driving software for Intel XScale CPU family. With only a JTAG connection, Jelie is able to upload a debug handler, initialize the memory, upload and debug programs.

Jelie can reach the JTAG port of the target processor trough a parallel port and a OCDemon McGraigor Wiggler adapter. USB connection using Anchor's EzUSB is also possible.

Jelie understands GDB's serial protocol on a TCP/IP port.

Jelie is released under the GNU General Public License (GPL).

Jelie connects GDB to XScale using JTAG port.

On what hardware does it work ?

Jelie runs on:

Jelie has been made for PXA250 and PXA255. We really do not know how it behaves with other XScale CPU.

How hard is it to adapt Jelie to a new system ?

The SDRAM controller is initialized by the debug handler of Jelie. It's hard coded and there is absolutely no autodetection. Get a new configuration from Intel web site. Read debugHandler/webconf.S and make your new memory controller configuration code look like it.

Remember that the debug handler is running from the instruction cache. You can't access code in data mode. Instruction like:
ldr r0, =0xFF00FF00
will NOT work. Use instead the macro lreg, defined in debugHandler/loadreg.S.

Online Documentation


jelie-1.4.tar.gz : K-Team release.
version 1.3 : with clean multiple hardware support for debugHandler.
version 1.2 : supporting step by step using hard breakpoints.
version 1.1 : first public release.

CVS access

You can access Jelie's source on CVS through savannah.
You can also have a look at the sources through ViewCVS.

About the authors

and are the authors of Jelie. It has been written at LAP, EPFL during winter 2002-2003. It's part of a diploma project.


Jelie has been design for a precise board: Armonie. It's free hardware. Have a look at its web site.